DocumentCode :
703984
Title :
Giant spin hall effect (GSHE) logic design for low power application
Author :
Yaojun Zhang ; Bonan Yan ; Wenqing Wu ; Hai Li ; Yiran Chen
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Pittsburgh, Pittsburgh, PA, USA
fYear :
2015
fDate :
9-13 March 2015
Firstpage :
1000
Lastpage :
1005
Abstract :
Conventional CMOS transistors will reach its power wall, a huge leakage power consumption limits the performance growth when technology scales down, especially beyond 45nm technology nodes. Spin based devices are one of the alternative computing technologies that aims to replace the current MOS based circuits by taking the advantage of their attractive characteristics, including non-volatility, high integration density and small cell area. The development of technologies such as spin-transfer torque random access memory (STT-RAM) and spin torque majority gate logic has become a story of great success. However, most of these technologies faces problems like, small operation margin, poor fan-out ability, etc. As the latest spin technology, Giant Spin Hall Effect (GSHE) Magnetic Tunneling Junction (MTJ) demonstrates a much better operation speed, switching probability and resistance margin. By leveraging the benefit of greater power efficiency and area density, GSHE MTJ elements become a suitable candidate for spintronic logic gates. Compare with traditional MOS transistors based logic gates, GSHE MTJ based logic can operate as a non-volatile memory and requires a much smaller number of elements to perform same logical operations (i.e., `AND´, `OR´, `NAND´ or `NOR´ gate.). And compare with other spin based logics, GSHE MTJ based logic also provides an better performance, excellent CMOS process compatibility and great fan-out ability.
Keywords :
CMOS memory circuits; logic design; logic gates; low-power electronics; magnetic tunnelling; power consumption; probability; random-access storage; spin Hall effect; switching circuits; CMOS process compatibility; CMOS transistors; GSHE MTJ based logic; GSHE MTJ elements; GSHE logic design; GSHE magnetic tunneling junction; MOS based circuits; MOS transistors based logic gates; NAND gate; NOR gate; STT-RAM; area density; computing technologies; giant spin Hall effect logic design; integration density; leakage power consumption; low power application; nonvolatile memory; power efficiency; resistance margin; spin based devices; spin based logics; spin torque majority gate logic; spin-transfer torque random access memory; spintronic logic gates; switching probability; Adders; CMOS integrated circuits; Logic gates; Resistance; Strips; Switches; Writing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
Conference_Location :
Grenoble
Print_ISBN :
978-3-9815-3704-8
Type :
conf
Filename :
7092536
Link To Document :
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