Device bias technique to improve design metrics of 6T SRAM cell for subthreshold operation

At present day SRAM cell is under renewal stage. Researchers are aiming to get an SRAM cell which is reliable and robust against process, voltage and temperature (PVT) fluctuations. An SRAM cell is also expected to support low-power applications. This article proposes a new way for designing an SRAM cell. The proposed cell functions properly even bellow subthreshold region. Therefore, it can be useful for ultralow-power applications. Robustness/reliability of the proposed design is investigated by estimating read static noise margin (RSNM). The estimated results are compared with its conventional counterpart. The proposed 6T SRAM cell offers 1.83× faster read operation. It is also less affected by PVT fluctuations (by 1.47×) during read operation compared to conventional 6T SRAM cell. The proposed SRAM cell exhibits 1.40× higher RSNM compared to conventional 6T SRAM cell, proving its reliability during read operation. It also shows 3.86% faster write operation. It is 18.4% less affected by PVT fluctuations. It has 2.33% higher write static noise margin (WSNM) than the conventional 6T SRAM cell.