Analysis and comparison of leakage power reduction techniques in CMOS circuits

This paper compares various leakage reduction techniques including Multi-threshold CMOS, Super-Cutoff CMOS, Zigzag, Stack Effect, Input Vector Control, LECTOR, Sleepy Stack, Sleepy Keeper, VCLEARIT, GALEOR, Dual Sleep, Sleepy-Pass Gate and Transistor Gating. The paper elaborately explores the working, comparison and analysis of all these techniques in different CMOS technologies. Leakage Power is analyzed during the standby mode of operation. It has been observed that for a particular circuit leakage depends on CMOS technology as well as leakage reduction technique. In this paper, wide range of results for leakage power reduction techniques of CMOS technologies from 180nm to 45nm is covered which will be helpful for further research in this area.