DocumentCode :
704718
Title :
An onboard digital transparent processor for a multi-beam satellite
Author :
Shah, Himanshu M. ; Mishra, Pramod ; Mishra, Neeraj ; Jain, Pratik ; Saiyed, Md Azhar ; Banik, Alak
Author_Institution :
Space Applic. Centre, Indian Space Res. Organ., Ahmedabad, India
fYear :
2015
fDate :
19-20 Feb. 2015
Firstpage :
366
Lastpage :
371
Abstract :
This paper describes an efficient design of digital transparent processor payload subsystem, developed at Space Applications Centre (ISRO) for a multi-beam, high throughput communication satellite. The digital transparent processor, also called digital mesh processor, onboard a multi-beam communication satellite performs the functions of slicing the uplink bandwidth into fine granules, switching it as per user requirements and combining the bandwidth-granules for downlink transmission. It effectively serves as exchange-in-the-sky providing inter-beam and intra-beam connectivity among users in various spot beams; the connectivity may be unicast, multicast or broadcast. The digital transparent processor has four main subsystems namely Frequency Demultiplexer, Channel Switch, Frequency Multiplexer and Mesh Network Manager. A design verification model of the digital transparent processor has been implemented and its design, hardware and software implementation details, simulation and hardware performance results are presented.
Keywords :
artificial satellites; demultiplexing equipment; multiplexing equipment; satellite communication; telecommunication network management; ISRO; Space Applications Centre; bandwidth-granules; channel switch subsystem; digital mesh processor; downlink transmission; exchangein-the-sky; frequency demultiplexer subsystem; frequency multiplexer subsystem; intrabeam connectivity; mesh network manager subsystem; multibeam high throughput communication satellite; onboard digital transparent processor payload subsystem; Bandwidth; Filter banks; Frequency division multiplexing; Payloads; Prototypes; Switches; Digital transparent processor; Xilinx Virtex-5 FPGA; digital mesh processor; onboard processing payload; transmultiplexer;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing and Integrated Networks (SPIN), 2015 2nd International Conference on
Conference_Location :
Noida
Print_ISBN :
978-1-4799-5990-7
Type :
conf
DOI :
10.1109/SPIN.2015.7095432
Filename :
7095432
Link To Document :
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