Efficient technique to reduce power dissipation of Op-Amps at high speed

To draw an accurate relationship between power dissipation and speed is a challenging problem in operational Amplifier with switch capacitance. However, transformation of current steer circuit into charge steer is an efficient technique to reduce power dissipation even at higher speed. In this paper, an efficient model is proposed to estimate the 1^st and 2^nd stage operational Amplifier´s power dissipation and delay, which can further used to design higher order Operational Amplifier, Voltage controlled Oscillator, Analog to Digital converters and other efficient power CMOS circuits. Analysis of 1^st and 2^nd stage Amplifier with BSIM4 model for CMOS in Tanner environment is done. The result shows that the power dissipation is reduced approximately 63% for 1^st stage and 53:5% for 2^nd stage Amplifier using charge steering technique at 90nm.