Evaluation of scalable 3-D Network on Chip architectures

The increase growth of VLSI technology and consumer demand has enabled future System-on-Chip (SoC) systems to integrate up to several hundreds of cores within a single chip. Due to such enormous integration density and complexity of the system-on-Chip (SoC), the conventional architectures are not suitable to fulfill the demand and scalability issues. The application of traditional network technologies in the form of Network-on-Chip is a potential solution; however it suffers from high speed. In this paper, we have discussed evaluated and proposed some 3-Dimensional scalable architecture for Network-on-Chip that has reduce diameter and degree.