GTL IO standards based WLAN specific low power ALU design on FPGA

This work deals with the designing of 802.11 WLAN Channel specific energy efficient ALU on FPGA. GTL IO standards are applied to the target design. This design is implemented on Virtex-5 and device XC5VLX50TFF1136. In this work, Xilinx 14.6 is used as a simulator, Verilog is used as a verification language and XPower is the power consumption estimator. There is 82.48%, 73.54%, 67.54%, 61.95% and 62.82% IO power reduction for 0.9GHz, 2.4GHz, 3.6GHz, 4.9GHz and 5.9GHz frequencies respectively when we migrate from GTLP_DCI IO standard to GTL IO standard. There is total power reduction of 65.39% for 0.9GHz frequency when we migrate from GTLP_DCI to GTL IO standard. There is 55.98%, 50%, 42.99% and 37.73% reduction in total power for the frequencies 2.4GHz, 3.6GHz, 4.9GHz and 5.9GHz respectively when we migrate from GTLP_DCI IO standard to GTLP IO standard.