Low power-area efficient design of 1 bit full adder

In nanometer design pattern, leakage power has a basic need of total power. Consumption of power have been increased as a priority in the aspect of design for every Integrated Circuits(IC). To an added note is a fundamental arithmetic operation is used frequently in many large scale as well as very large scale integration application oriented DSP and microprocessor designs. The Full adder circuit design is the very basic and indeed unit of an ALU, which decides the system´s overall behaviour. The power consumption of a processor is fully depends on the ALU, so the power consumed by the full adder circuit in the ALU should get partially reduced to match up the needs of a designer and so it will be called as “a efficiently less powered design”. This full adder design is of low powered and transistors of less count. which is verified using Micro wind simulations. The circuit design is of 6T and with pass transistor logic. The power of this circuit is tremendously less when compared to the previously designed adder circuit which is of 28T and 8T static and energy recovery full adder (SERF) design, whereas the delay is comparatively less.