HSTL I/O standard based environment friendly energy efficient ROM design on FPGA

In order to extend the battery life and gain in term of portability, there is always a research gap in low power processor design. In order to complete low power processor design project, there is need to re-design each and every part of processor with low power techniques. Selection of energy efficient I/O standard is also playing a significant role in energy efficient design. In this work, we are using High Speed Transceiver Logic (HSTL) in energy efficient ROM design on Virtex-5 FPGA using Verilog hardware description language and Xilinx ISE simulator. Here, we use six different HSTL IO Standards. These are: HSTL_I, HSTL_II, HSTL_III, HSTL_III_18, HSTL_III_DCI, and HSTL_II_18. For each IO standard, we are going to run our ROM design with 1.0GHz, 2.9GHz, 3.3GHz, 3.6GHz, 3.8GHz and 4.0GHz device operating frequency. With dynamic frequency scaling, we are saving 92.18% clock power, 100% signal power, and 9.82% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but HSTL_III_DCI having 39.06%, 9.21%, 25.88%, 25.88%, 9.21% more I/O power consumption with respect to HSTL_I, HSTL_II, HSTL_III, HSTL_III_18, HSTL_II_18 respectively at 3.3GHz frequency.