Area & power optimization of VPB peripheral memory for ARM7TDMI based microcontrollers

In recent years, on chip memory is one of the most vital part of advanced microcontrollers and its organization (i.e. distribution of registers) greatly impact the power and performance of device. So in this paper, we propose a schematic approach for effective memory distribution which leads to reduction in energy consumption of ARM7TDMI processor. Improvement is attained by using a model that resizes the SRAM allocated for VPB peripherals by rearranging the reserved and other useful bits in VPB peripherals registers, thus reducing the number of overall bits in the memory. The proposed SRAM design is simulated and implemented using PSPICE. The base technology used for this analysis is a 22 nm CMOS process. Thus optimal use of registers in terms of size and power is achieved.