Automatic synthesis of combinational circuits set for the purposes of FPGA reconfiguration within the model of partial failures of logic elements

The article considers the problem of programmable logic device reconfiguration after a failure of logic elements. The task is relevant to areas such as space exploration and important industrial facilities management that use highly reliable fault-tolerant systems. The article considers the partial failures of logic elements in the configurable logic blocks. Partially failed element retains some functionality and can still be used. This article describes reconfiguration algorithms. Since the reconfiguration algorithms return correct scheme, one can say that algorithms for the synthesis of combinational circuits have also been developed.