Title :
Digitally assisted low-power pipelined analog-to-digital converters
Author :
Piatak, Ivan ; Morozov, Dmitry ; Pilipko, Mikhail
Author_Institution :
Dept. of the Integrated Electron., St. Petersburg Polytech. Univ., St. Petersburg, Russia
Abstract :
In this paper the main aspects in construction of the low-power CMOS pipelined analog-to-digital converters (ADCs) are discussed. The main requirements for a 1.5 bit redundant stage of the pipeline ADC are defined. Examples of the digital and the analog error correction mechanisms for the pipelined ADC in conjunction with the power reduction mechanisms are considered.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; low-power electronics; pipeline arithmetic; digitally assisted; error correction mechanisms; low-power CMOS pipelined ADC; low-power pipelined analog-to-digital converters; power reduction mechanisms; CMOS integrated circuits; CMOS technology; DH-HEMTs; Semiconductor device modeling; 1.5 bit redundant stage; SC-circuits; digital error correction; multiplying DAC; operational amplifier; pipelined ADC;
Conference_Titel :
Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW), 2015 IEEE NW Russia
Conference_Location :
St. Petersburg
Print_ISBN :
978-1-4799-7305-7
DOI :
10.1109/EIConRusNW.2015.7102273
