A controllable setup and propagation delay flip-flop design

Author

Giron-Allende, Alexandro ; Avendano, Victor ; Martinez-Guerrero, Esteban

Author_Institution

Freescale Semicond., Guadalajara, Mexico

fYear

2015

fDate

25-27 March 2015

Firstpage

1

Lastpage

5

Abstract

A Controllable flip flop design for sequential synchronous systems is proposed. The flip-flop setup time and propagation delay is controlled with an additional setup time and delay control (SDC) input. With this SDC enable, it is possible to enhance the circuit timing performance when required. In this paper, it is shown that when the SDC input is enabled, the flip-flop setup time and Clk-Q propagation delay are reduced, and when the SDC control remains disabled, the flip-flop reduces its timing margin saving power. The proposed flip-flop is designed and characterized in a TSMC 28 nm bulk CMOS technology.

Keywords

CMOS logic circuits; delays; flip-flops; logic design; sequential circuits; timing; Clk-Q propagation delay; TSMC bulk CMOS technology; circuit timing performance; delay control input; propagation delay flip-flop design; sequential synchronous systems; setup time input; size 28 nm; Clocks; Delays; Flip-flops; Inverters; Power demand; Propagation delay; CMOS sequential circuits; controllable; flip-flop; high speed; low power; setup time; timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (LATS), 2015 16th Latin-American

Conference_Location

Puerto Vallarta

Type

conf

DOI

10.1109/LATW.2015.7102412

Filename

7102412