Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability

Bias Temperature Instability (BTI) has become a major issue for circuit reliability in deeply scaled CMOS technologies. Due to BTI, circuit delay increases as time progress, which may lead to a timing constraint violation. This paper proposes an efficient metric to select the most favorable gates to be resized to enhance circuit reliability. A close analysis is devoted to the main aspects allowing to identify the most favorable gates to be resized. The metric introduces a composited point of view of gate delay sensitivity to channel width sizing, which reflects the sizing impact on the initial gate delay and gate delay degradation. Other parameters are also considered to improve the metric effectiveness. The proposed metric has been applied in some ISCAS85 benchmark circuits along with an iterative gate-selection and gate-sizing procedure. The results show that our proposal is suitable to achieve higher product reliability with minimum area overhead.