Design dependent SRAM PUF robustness analysis

Author

Cortez, Mafalda ; Hamdioui, Said ; Ishihara, Ryoichi

Author_Institution

Fac. of EE, Math. &CS, Delft Univ. of Technol., Delft, Netherlands

fYear

2015

fDate

25-27 March 2015

Firstpage

1

Lastpage

6

Abstract

In this paper we evaluate and compare the robustness (i.e., repeatablilty and uniqueness) of two SRAM PUF designs, General putpose (GP) and Low-Power (LP), by means of both circuit simulatios and industrial measurements. Circuit simulations are performed on both designs while considering two technology nodes (45nm and 32nm), three temperatures and three voltage ramp-up times. Industrial measurements are preformed to validate the simulation results. The silulation results as well as industrial measurements demonstrate that GP devices provide better repeatablilty for all investigated cases (up to 4.5X better) while the uniquenesss is design independent.

Keywords

SRAM chips; integrated circuit design; low-power electronics; GP design; LP design; SRAM PUF robustness analysis; circuit simulation; general purpose design; low-power design; size 32 nm; size 45 nm; temperature ramp-up time; voltage ramp-up time; Decision support systems; Erbium; Error correction codes; Measurement; Nonvolatile memory; Random access memory; Robustness; PUF-based system; Robustness; SRAM PUF;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (LATS), 2015 16th Latin-American

Conference_Location

Puerto Vallarta

Type

conf

DOI

10.1109/LATW.2015.7102498

Filename

7102498