FPGA redundancy recovery based on partial bitstreams for multiple partitions

Author

Goncalves Martins, Victor M. ; Reis, Joao Gabriel ; Netoy, Horacio C. C. ; Augusto Bezerra, Eduardo

Author_Institution

Dept. of Electr. & Electron. Eng., Fed. Univ. of Santa Catarina, Florianόpolis, Brazil

fYear

2015

fDate

25-27 March 2015

Firstpage

1

Lastpage

4

Abstract

The Triple Modular Redundancy (TMR) strategy is a common and good option for a system to recover from possible faults. However, in case of a permanent fault in the TMR hardware, the redundancy advantage can be destroyed. In this paper, we present a low cost solution to enable Fault Detection, Isolation and Recovery (FDIR) in a TMR system. Our methodology uses the Assisted Design Flow (ADF) that implements Partial Bitstream for Multiple Partitions (PB4MP). This method allows to relocate modules in different Reconfigurable Partitions (RPs) using only one bitstream per module. The results show that with a minor increase in the program memory of the digital design, it is possible to increase considerably the TMR availability.

Keywords

fault diagnosis; field programmable gate arrays; logic design; redundancy; ADF; FDIR; FPGA redundancy recovery; PB4MP; TMR strategy; assisted design flow; digital design; fault detection; fault isolation; fault recovery; partial bitstream for multiple partitions; permanent fault; program memory; reconfigurable partitions; triple modular redundancy strategy; Field programmable gate arrays; Hardware; Memory management; Random access memory; Redundancy; Routing; Tunneling magnetoresistance; Bistream for Multiple Partitions; FPGA Recovery;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (LATS), 2015 16th Latin-American

Conference_Location

Puerto Vallarta

Type

conf

DOI

10.1109/LATW.2015.7102500

Filename

7102500