Using only redundant modules with approximate logic to reduce drastically area overhead in TMR

The use of Triple Modular Redundancy (TMR) with majority voters can guarantee full single fault masking coverage for a given circuit against transient faults. However, it presents a minimum area overhead of 200% compared to the original circuit. In order to reduce area overhead drastically without compromising significantly the fault coverage, TMR can use approximated logic circuits approach to generate redundant modules that are optimized in area compared to the original module. In this work, we propose the use of only approximate logic modules to compose the TMR in order to reduce the area overhead close to zero percent. We use a boolean factoration method to compute approximate functions and to select the best combinations of approximate logic. The circuits are implemented in complex gates and we employ structural reorder techniques to target the highest fault coverage. All the tests are done using a fault injection tool designed specifically to cope with logic gate and transistor description level. Results show that area overhead can be reduced from 200% to 120% and still reaching fault coverage of more than 95%. And when reaching 0% of area overhead, fault coverage masking can reach 75%.