Energy analysis and performance evaluation of GaN cascode switches in an inverter leg configuration

This paper presents an analysis of the energy loss distribution in a cascode array and a study of the behavior of two GaN cascode devices in an inverter leg configuration. A simple model of the cascode connection is developed to get estimations of energy losses and its accuracy is validated through experimental measurements using a Double Pulse Tester (DPT). The simple model is then applied to analyze the energy loss distribution between the two devices within the cascode switch during turn-off and turn-on. The analysis shows that most of the energy involved in the turn-off process is stored and that most of the energy is dissipated in the GaN HEMT during turn-on. The results are compared against other device combinations including silicon super junction technology. The analysis shows that two GaN cascode devices in an inverter leg configuration represent an improvement over the Si MOSFET plus SiC diode combinations reducing the energy losses up to 26 percent at high current conditions and eliminating the requirement for body diode suppression and the use of an external SiC diode. The switching losses of a single GaN device and SiC diode were shown to be 40 percent lower than the latest generation super junction Si MOSFET.