Design of DC-side stray inductance for high speed switching inverter based on normalization procedure

This paper presents a design procedure for the DC-side stray inductance in a high-speed switching circuit based on a normalization procedure. It is shown that the normalization procedure can define the relationship between the inverter power rating and the upper and lower limitations of the stray inductance. It is clear that the upper limitation of the stray inductance depends on the voltage and current rating of the inverter circuit, and the acceptable over-voltage value is also determined by the voltage rating of the power device. In addition, the lower limitation of the stray inductance considering the short-circuit current is determined by the current rating of the power device. The stray inductance is shown not as the absolute value [H] but as the percent value [%], therefore, it can be designed depending on the inverter power rating. In order to verify the analysis results, experiments using a SiC-MOSFET and SiC-SBD are conducted.