DocumentCode :
708667
Title :
Reduction of overhead in adaptive body bias technology due to triple-well structure based on measurement and simulation
Author :
Ogasahara, Yasuhiro ; Sekigawa, Toshihiro ; Hioki, Masakazu ; Nakagawa, Tadashi ; Tsutsumi, Toshiyuki ; Koike, Hanpei
Author_Institution :
Nat. Inst. of Adv. Ind. Sci. & Technol.(AIST), Tsukuba, Japan
fYear :
2015
fDate :
23-26 March 2015
Firstpage :
207
Lastpage :
211
Abstract :
This paper presents the significant reduction of the area overhead due to triple-well structure for adaptive body bias methods. Triple-well TEGs which include violation of design rules originating from voltage tolerance were implemented on a 65nm process. Reexamining voltage tolerance based on measurement results reduced deep n-wells spacing by 60% on the 65nm process. A new method for further overhead reduction is proposed based on a device simulation which is validated with measurement results.
Keywords :
CMOS integrated circuits; integrated circuit design; CMOS process; adaptive body bias technology; area overhead reduction; deep n-wells spacing; design rules; size 65 nm; triple-well TEGs; triple-well structure; voltage tolerance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures (ICMTS), 2015 International Conference on
Conference_Location :
Tempe, AZ
ISSN :
1071-9032
Print_ISBN :
978-1-4799-8302-5
Type :
conf
DOI :
10.1109/ICMTS.2015.7106154
Filename :
7106154
Link To Document :
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