DocumentCode
709263
Title
Memory efficient global scheduling of real-time tasks
Author
Alhammad, Ahmed ; Wasly, Saud ; Pellizzoni, Rodolfo
Author_Institution
Univ. of Waterloo, Waterloo, ON, Canada
fYear
2015
fDate
13-16 April 2015
Firstpage
285
Lastpage
296
Abstract
Current computing architectures are commonly built with multiple cores and a single shared main memory. Even though this architecture increases the overall computation power, main memory can easily become a bottleneck. Simultaneous access to main memory from multiple cores can cause both (1) severe degradation in performance and (2) unpredictable execution time for real-time applications. We propose in this paper to mitigate these two problems by co-scheduling cores as well as the main memory for predictable execution. In particular, we use a DMA component to overlap memory with computation for hiding the memory latency and therefore increasing the system performance. The main contribution of this paper is a novel global co-scheduling algorithm along with its associated schedulability analysis for sporadic hard real-time tasks. We evaluated our system by generating synthetic tasksets based on real benchmark parameters. The results show a significant improvement in system utilization while retaining a predictable system behavior.
Keywords
real-time systems; scheduling; shared memory systems; DMA component; associated schedulability analysis; co-scheduling cores; memory efficient global scheduling; memory latency; multiple cores; shared main memory; sporadic hard real-time task; synthetic taskset generation; Interference; Loading; Multicore processing; Processor scheduling; Real-time systems; Schedules;
fLanguage
English
Publisher
ieee
Conference_Titel
Real-Time and Embedded Technology and Applications Symposium (RTAS), 2015 IEEE
Conference_Location
Seattle, WA
Type
conf
DOI
10.1109/RTAS.2015.7108452
Filename
7108452
Link To Document