Multi-fidelity design optimization of planar inductors with Sonnet

Low-cost design optimization of a planar inductor realized in a 65-nm CMOS technology is presented. Our approach exploits variable-fidelity electromagnetic (EM) inductor models implemented in Sonnet em, a pattern search algorithm, and design refinement based on the output space mapping technology with local polynomial approximations used as an underlying low-fidelity model. The optimized design has been obtained at the cost of a few high-fidelity EM simulations of the inductor.