DocumentCode
709584
Title
Compact thermal model for microprocessor package based on one-dimensional thermal network with average temperature nodes
Author
Nishi, Koji ; Hatakeyama, Tomoyuki ; Nakagawa, Shinji ; Ishizuka, Masaru
Author_Institution
AMD Japan Ltd., Tokyo, Japan
fYear
2015
fDate
14-17 April 2015
Firstpage
132
Lastpage
137
Abstract
This paper proposes a new compact thermal model (CTM) for the microprocessor package based on a one-dimensional thermal network with average temperature nodes. Different from the two-resistor model and the DELPHI model, the proposed CTM doesn´t assume an isothermal surface, but sets plate heat sources along the top surface of the silicon die and the bottom surface of the solder balls layer. It is found that the temperature prediction result by a thermal network with the proposed CTM matches the three-dimensional heat conduction simulation result closely through a numerical experiment of a microprocessor system with a heat sink fan.
Keywords
elemental semiconductors; heat conduction; heat sinks; microprocessor chips; silicon; thermal management (packaging); 1D thermal network; 3D heat conduction simulation; DELPHI model; Si; average temperature node; compact thermal model; heat sink fan; microprocessor package; silicon die; solder balls layer; temperature prediction; two-resistor model; Electronic packaging thermal management; Heat transfer; Heating; Microprocessors; Silicon; Thermal resistance; compact thermal model (CTM); microprocessor; simplified boundary condition model; thermal network;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging and iMAPS All Asia Conference (ICEP-IACC), 2015 International Conference on
Conference_Location
Kyoto
Print_ISBN
978-4-9040-9012-1
Type
conf
DOI
10.1109/ICEP-IAAC.2015.7111014
Filename
7111014
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