Opto-electronic hybrid integrated chip packaging technology for silicon photonic platform using gold-stud bump bonding

We propose a new solder-free and low-temperature (200 °C or less) flip-chip integration technology for silicon photonic platforms. Au stud bumps are arranged facing each other on a substrate and a chip. Plastic deformation when the bumps are heated and pressed achieves Au-Au bonding. We measured mechanical and electrical characteristics (bonding strength, electrical resistance, and high-frequency characteristics) of test samples fabricated by using this technology and confirmed good performance. Further, we fabricated a four-channel WDM receiver using this technology and confirmed its good performance at 25-Gbit/s operation.