Silicon level circuit implementation for system-on-chip power integrity improvement

As microprocessor market is expanding and moving toward tablet and smart phone segment, the conventional power integrity design practice which is placing package and board capacitor to stabilize voltage supply is no longer a favorable solution. Due to z height challenge, adding an ultra-low profile capacitor at platform level becomes an expensive solution. Hence, power integrity design has to evolve from current platform level power delivery network design toward governing the root of AC noise at silicon level. In this paper, silicon level circuit implementation for system-on-chip power integrity improvement is proposed and discussed. In addition, its impact towards power integrity noise is also enveloped for design references.