• DocumentCode
    709831
  • Title

    SOI FinFET soft error upset susceptibility and analysis

  • Author

    Oldiges, P. ; Rodbell, K.P. ; Gordon, M. ; Massey, J.G. ; Stawiasz, K. ; Murray, C. ; Tang, H. ; Kim, K. ; Muller, K.P.

  • Author_Institution
    SRDC, IBM Corp., Hopewell Junction, VA, USA
  • fYear
    2015
  • fDate
    19-23 April 2015
  • Abstract
    Measurements of the soft error upset cross section for SOI FinFET SRAMs are compared to earlier generation PDSOI SRAMs, with the FinFET circuit showing 2-3 orders of magnitude lower soft error susceptibility. This improvement is shown by simulations to be due to the better electrostatic control of the channel in the FinFET.
  • Keywords
    MOS integrated circuits; SRAM chips; electrostatics; radiation hardening (electronics); silicon-on-insulator; PDSOI SRAM; SOI FinFET SRAM; SOI FinFET soft error upset susceptibility; electrostatic control; soft error upset cross section; Error analysis; FinFETs; Integrated circuit modeling; Inverters; Latches; Measurement uncertainty; Random access memory; FinFET; Measurements; PDSOI; Simulations; Soft Error Upset;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium (IRPS), 2015 IEEE International
  • Conference_Location
    Monterey, CA
  • Type

    conf

  • DOI
    10.1109/IRPS.2015.7112729
  • Filename
    7112729
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=709831