Device performance analysis on 20nm technology thin wafers in a 3D package

Author

Kannan, Sukeshwar ; Agarwal, Rahul ; Bousquet, Arnaud ; Aluri, Geetha ; Hui-Shan Chang

Author_Institution

GLOBALFOUNDRIES US Inc., Malta, NY, USA

fYear

2015

fDate

19-23 April 2015

Abstract

This paper presents the impact of wafer thinning process on GLOBALFOUNDRIES high-k metal gate CMOS wafers with TSV. The initial study of wafer backside surface finish and thickness was performed on non-TSV wafers, and the impact on active devices such as: MOS (metal-oxide semiconductor) capacitors, ring oscillators, analog circuit performance and front end of line (FEOL) reliability macros was characterized. Based on the experimental results, a suitable wafer surface finish and thickness was selected for TSV wafer processing. The impact of wafer thinning on device performance was monitored at various stages of packaging, including before thinning, after thinning, end-of line (EOL), and post package reliability tests.

Keywords

CMOS analogue integrated circuits; integrated circuit reliability; surface finishing; three-dimensional integrated circuits; wafer level packaging; 3D packaging; EOL; FEOL reliability test; GLOBALFOUNDRIES high-k metal gate CMOS wafers; MOS capacitors; active devices; analog circuit performance; device performance analysis; front end of line reliability; metal-oxide semiconductor capacitors; non TSV wafer processing; ring oscillators; size 20 nm; wafer backside surface finishing; wafer thinning process; Current measurement; Field effect transistors; Performance evaluation; Semiconductor device reliability; Stress; Three-dimensional displays; 3D package; device characterization; package reliability; through silicon via (TSV); wafer thinning;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2015 IEEE International

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/IRPS.2015.7112735

Filename

7112735