Scenario for catastrophic failure in interconnect structures under chip package interaction

This paper describes the critical importance of interfacial strength between copper lines and cap layer for catastrophic failure due to chip-package interaction (CPI). Recently, copper interconnects and insulating layers are stacked alternately in semiconductor devices. Especially, copper/low-k structures are widely selected. However, the low-k materials have weak mechanical properties, which sometimes induces reliability issues, especially, chip package interactions. In our previous works, the interfacial strength of Cu/Cap has been successfully measured on the sub-micron scale. In this paper, based on the measured results, we try to simulate the initiation and propagation of failure in interconnect structures and discuss the scenario for catastrophic failure under CPI.