Threading dislocations in III-V semiconductors: Analysis of electrical conduction

The implementation of devices with high mobility substrates requires growing III-V semiconductors over the underlying silicon substrates. However, due to the lattice mismatch, III-V materials tend to develop a significant density of structural defects, which may affect the device electrical characteristics. In this study, Threading Dislocation (TD) defects, which may propagate through the III-V layers, were studied using Conductive Atomic force Microscopy (CAFM). This technique is shown to be effective for identification and analysis at the nanoscale of the pre- and post-electrically stressed TD. The TD conduction studied at different temperatures (T) is shown to be consistent with the Poole-Frenkel (PF) emission process.