Contact resistance of solder bump with low cost photosensitive polyimide for high performance SoC

Author

Jongwoo Park ; Jungpyo Hong ; Miji Lee ; Dongyoon Sun ; Kyung Kang ; Taesung Kim ; Seungwon Kim ; Sujin Kwon ; Changkyu Joo ; Sangsu Ha ; Wooyeon Kim ; Jongsu Ryu ; Sangwoo Pae

Author_Institution

Quality & Reliability, Samsung Electron. Co., Ltd., Yongin, South Korea

fYear

2015

fDate

19-23 April 2015

Abstract

One of technical hurdles in far back-end of line (FBEOL) process is to assure lower solder bump contact resistance (Rc) associated with photosensitive polyimide (PSPI) and under bump metal (UBM) process. Often, higher bump Rc results in low Vcc shift fails in high performance SoC product. With palpable understanding of outgassing behaviors of PSPI and meticulous characterization of degassing phenomena linked to plasma etch with physical vapor deposition (PVD), we successfully achieved <; 10mΩ bump Rc even with a low cost PSPI without an existing PVD refurbishment. From photo process to package reliability, a far back-end process optimization for cost effective bump production will be presented.

Keywords

contact resistance; outgassing; polymers; solders; sputter etching; system-on-chip; vapour deposition; FBEOL process; PSPI; PVD; UBM process; contact resistance; far back-end of line process; high performance SoC; low cost photosensitive polyimide; outgassing behavior; package reliability; physical vapor deposition; plasma etch; solder bump; system-on-chip; under bump metal; Optimization; Plasmas; Reliability; Rough surfaces; Surface morphology; Surface roughness; Surface treatment; Bump resistance; far back-end-of line process; outgassing; photosenstive polyimide; physical vapor desposition; reliability qualification; residual gas analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2015 IEEE International

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/IRPS.2015.7112790

Filename

7112790