A novel high level ESD FDNSCR with drain side engineering in PMIC application

In order to develop cost-effective System-on-Chip (SoC) solutions, it is important to implement High-Voltage (HV) tolerant devices using standard CMOS technologies for varied applications, such as display and LED drivers, flash memories, automotive applications etc. However, the on-chip ESD protection designs are required to provide higher robustness to prevent chip from ESD damage. Silicon Controlled Rectifiers (SCR) have been widely used, because of their superior area-efficient ESD robustness [1-3]. However, lower failure current It2 has been observed during ESD stress on Field Drift MOSFET Silicon Controlled Rectifier (FDNSCR) devices in 0.18μm BCD epi process. The root cause of early failure is related to low turn-on efficiency of SCR during ESD stress.