Extended TDDB power-law validation for high-voltage applications such as OTP memories in High-k CMOS 28nm FDSOI technology

Author

Benoist, A. ; Denorme, S. ; Federspiel, X. ; Allard, B. ; Candelier, P.

Author_Institution

Ampere INSA Lyon, Univ. de Lyon, Villeurbanne, France

fYear

2015

fDate

19-23 April 2015

Abstract

This paper aims to provide reliability projections and modeling for wearout current consumption and oxide lifetime (or programming time) under programming conditions regarding OTP memories perimeter. TDDB reliability methodology have been carried out to high voltages and the power law dependent T_BD equations terms have been discussed. Adjustments focusing on the temperature impact on voltage acceleration offer us a compact model for TDDB HV.

Keywords

CMOS memory circuits; elemental semiconductors; integrated circuit modelling; integrated circuit reliability; power integrated circuits; silicon; silicon-on-insulator; OTP memory perimeter; Si; TDDB reliability methodology; extended TDDB power-law validation; high-k CMOS FDSOI technology; high-voltage application; oxide lifetime; power law dependent T_BD equation; size 28 nm; wearout current consumption; Capacitors; Electric breakdown; High K dielectric materials; Logic gates; Mathematical model; Reliability; Temperature measurement; Antifuse; Area scaling; FDSOI; Fowler-Nordheim; High Voltage; High-k; OTP; TDDB; Weibull; wearout;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2015 IEEE International

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/IRPS.2015.7112804

Filename

7112804