Impact of DC and RF non-conducting stress on nMOS reliability

The increase of leakage current in deep-submicrometer MOS transistors operated below threshold is becoming a reliability concern for scaled technology nodes. Especially high-power analog applications like high efficiency PAs and RF-switches undergo to strong lateral field when V_g <;V_th. Indeed an increased degradation for these MOS applications was already reported in the state of the art but not completely understood. In this paper a thorough study of the DC non-conducting (NC) stress is presented and a new physical model describing the worsening of the electrical parameter is proposed. This model is suitable for being extended to the high frequency regime by means of a quasi-static sum (QS). For the first time RF stress measurements are conducted in various NC configurations. No frequency dependency is detected up to 4Ghz and the QS model is able to precisely predict the performance degradation.