FPGA realization and performance evaluation of fixed-width modified Baugh-Wooley multiplier

Fixed-width multipliers are widely used in digital signal processing (DSP) applications such as finite impulse response filter (FIR), fast Fourier transform (FFT) and discrete cosine transform (DCT). Baugh-Wooley multiplier is a preferred choice for the realization of 2´s complement multiplication operation used in these applications. This paper presents the hardware realization and performance evaluation of 8×8 fixed-width modified Baugh-Wooley multiplier using state-of-the-art 7 series field programmable gate arrays (FPGAs) such as Virtex-7, Artix-7 and Zynq-7000, available from Xilinx. Different optimization goals are applied to the multiplier design and the performance is evaluated for area, speed and power. Simulation is done to verify the functionality of the design.