Title :
FPGA realization and performance evaluation of fixed-width modified Baugh-Wooley multiplier
Author :
Badawi, Aiman ; Alqarni, Ali ; Aljuffri, Abdullah ; BenSaleh, Mohammed S. ; Obeid, Abdulfattah M. ; Qasim, Syed Manzoor
Author_Institution :
Nat. Center for Electron. & Photonics Technol., Commun. & Inf. Technol. Res. Inst., Riyadh, Saudi Arabia
fDate :
April 29 2015-May 1 2015
Abstract :
Fixed-width multipliers are widely used in digital signal processing (DSP) applications such as finite impulse response filter (FIR), fast Fourier transform (FFT) and discrete cosine transform (DCT). Baugh-Wooley multiplier is a preferred choice for the realization of 2´s complement multiplication operation used in these applications. This paper presents the hardware realization and performance evaluation of 8×8 fixed-width modified Baugh-Wooley multiplier using state-of-the-art 7 series field programmable gate arrays (FPGAs) such as Virtex-7, Artix-7 and Zynq-7000, available from Xilinx. Different optimization goals are applied to the multiplier design and the performance is evaluated for area, speed and power. Simulation is done to verify the functionality of the design.
Keywords :
digital arithmetic; field programmable gate arrays; logic design; multiplying circuits; 7 series field programmable gate arrays; Artix-7 FPGA; FPGA realization; Virtex-7 FPGA; Xilinx; Zynq-7000 FPGA; fixed-width modified Baugh-Wooley multiplier; multiplier design; performance evaluation; two´s complement multiplication operation; Digital signal processing; Field programmable gate arrays; Finite impulse response filters; Optimization; Performance evaluation; Table lookup; Timing; Baugh-Wooley; FPGA; fixed-width; multiplier;
Conference_Titel :
Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE), 2015 Third International Conference on
Conference_Location :
Beirut
Print_ISBN :
978-1-4799-5679-1
DOI :
10.1109/TAEECE.2015.7113618
