Title :
Efficient highly-parallel turbo decoder for 3GPP LTE-Advanced
Author :
Jing-Shiun Lin ; Ming-Der Shieh ; Chung-Yen Liu ; Der-Wei Yang
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan
Abstract :
Turbo codes have been widely adopted in latest wireless communication systems due to their excellent error correction capability. In 3GPP LTE-Advanced systems, a peak data rate of up to 1 Gbps should be satisfied. To meet this throughput requirement, several turbo decoding algorithms aimed at achieving highly parallel architecture have been investigated. However, the resulting hardware cost of turbo decoders is increased considerably with increasing parallelism. This paper presents a modified parallel-window decoding algorithm to reduce the warm-up computation ratio per each decoding window. In addition, a dual-mode computing schedule is proposed to support the requirement of various code rates and block lengths. Experimental results reveal that the proposed design, implemented in the TSMC 90-nm CMOS process, can achieve the highest throughput rate of 1.45 Gbps and improve the normalized area efficiency by about 24.53% compared to the existing 3GPP-LTE-Advanced turbo decoders.
Keywords :
3G mobile communication; CMOS integrated circuits; Long Term Evolution; decoding; error correction codes; parallel architectures; telecommunication computing; turbo codes; 3GPP LTE-advanced system; Long Term Evolution; TSMC CMOS process; bit rate 1.45 Gbit/s; error correction capability; hardware cost; highly-parallel turbo decoder efficiency; parallel window decoding algorithm; size 90 nm; third generation partnership project; turbo codes; turbo decoding algorithm; wireless communication system; Algorithm design and analysis; Decoding; Iterative decoding; Measurement; Memory management; Parallel processing; Throughput;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-DAT.2015.7114513
