A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizer

A 3^rd-order 3-bit continuous-time delta-sigma modulator incorporating several techniques for performance enhancement is presented. In the quantizer, a proposed 3-bit two-step time-domain quantizer is used to facilitate lower power consumption and smaller chip area. In the loop filter, a single-opamp-biquad technique is adopted to realize a 3^rd-order loop filter to reduce the modulator power consumption. With an 8MHz bandwidth and 256-MHz sampling rate, the measured peak SNDR and dynamic range for this 3^rd-order modulators are 69.6 and 73 dB, respectively. Fabricated in a 90-nm CMOS, the chip consumes 5.01 mW from 1.2-V/1.6-V supply voltages. The FoM is 127 fJ/conversion.