An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction

Author

Che-Min Huang ; Tsung-Te Liu ; Tzi-Dar Chiueh

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2015

fDate

27-29 April 2015

Firstpage

1

Lastpage

4

Abstract

This paper presents a timing error resilient flip-flop (ERFF) circuit with high energy-efficiency. The proposed flip-flop design automatically corrects timing errors and therefore minimizes the performance degradation due to variations. The simulation results show that the proposed design can achieve better energy-efficiency in ISCAS´89 benchmark circuits and LEON3 integer-processing unit, when compared to other state-of-the-art timing error detection and correction methods.

Keywords

error correction; error detection; flip-flops; logic design; ERFF circuit; ISCAS´89 benchmark circuits; LEON3 integer-processing unit; energy-efficient resilient flip-flop circuit; flip-flop design; timing error resilient flip-flop circuit; timing-error correction method; timing-error detection method; CMOS integrated circuits; Clocks; Energy efficiency; Flip-flops; Latches; Pipelines; Timing; DVFS; energy efficient; flip-flop; timing error detection and correction; wide-operating voltage processor;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-DAT.2015.7114574

Filename

7114574