Nonlinear dynamic analysis and chip implementation of a new chaotic oscillator

A new four-dimensional chaotic oscillator is proposed in this paper. Circuit behavior model, synchronization with uncertain chaotic parameters and nonlinear dynamic analysis of the chaotic oscillator are presented. Furthermore, an analog circuit of the chaotic oscillator is implemented on a chip for the system-on-chip encrypted communication application. The entire chip area occupies 1.50 mm × 1.23 mm in 0.35 μm CMOS process with power dissipation of 360mW from a 1.4 V supply voltage.