Abstract :
As the economics of traditional devices scaling changes, alternative solutions to increase transistor counts in semiconductor packages are being explored, including various multi-die integration techniques. These solutions include 3D die stacking, 2.5D with dies sitting side-by-side on substrate, Package-on-Package (PoP), System in Package (SiP), etc. In particular, 2.5D and 3D device integration may create new challenges and old challenges seen in multi-chip module (MCM) manufacturing also re-appear to affect new users.
