Title :
At-Product-Test Dedicated Adaptive supply-resonance suppression
Author :
Taniguchi, Kohki ; Miura, Noriyuki ; Hayashi, Taisuke ; Nagata, Makoto
Author_Institution :
Grad. Sch. of Syst. Inf., Kobe Univ., Kobe, Japan
Abstract :
This paper presents an adaptive supply-resonance (SR) suppression scheme at a product testing stage. Dedicated to each product in different assembly forms, an on-chip power-delivery-network analyzer identifies SR frequency and autotunes notch filter for SR noise suppression. The feasibility has been silicon-proven by a prototype demonstration in 0.18μm CMOS successfully.
Keywords :
CMOS integrated circuits; circuit noise; circuit resonance; interference suppression; notch filters; power supply circuits; CMOS; SR frequency; SR noise suppression; adaptive SR suppression scheme; adaptive supply-resonance suppression; notch filter; on-chip power-delivery-network analyzer; product testing; Impedance; Monitoring; Noise; System-on-chip; Timing; Tuning; Voltage measurement;
Conference_Titel :
VLSI Test Symposium (VTS), 2015 IEEE 33rd
Conference_Location :
Napa, CA
DOI :
10.1109/VTS.2015.7116273
