DocumentCode :
7107
Title :
Countering Power Analysis Attacks UsingReliable and Aggressive Designs
Author :
Avirneni, Naga Durga Prasad ; Somani, Arun K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Volume :
63
Issue :
6
fYear :
2014
fDate :
Jun-14
Firstpage :
1408
Lastpage :
1420
Abstract :
Recent events have indicated that attackers are banking on side-channel attacks, such as differential power analysis (DPA) and correlation power analysis (CPA), to exploit information leaks from physical devices. Random dynamic voltage frequency scaling (RDVFS) has been proposed to prevent such attacks and has very little area, power, and performance overheads. But due to the one-to-one mapping present between voltage and frequency of DVFS voltage-frequency pairs, RDVFS cannot prevent power attacks. In this paper, we propose a novel countermeasure that uses reliable and aggressive designs to break this one-to-one mapping. Our experiments show that our technique significantly reduces the correlation for the actual key and also reduces the risk of power attacks by increasing the probability for incorrect keys to exhibit maximum correlation. Moreover, our scheme also enables systems to operate beyond the worst-case estimates to offer improved power and performance benefits. For the experiments conducted on AES S-box implemented using 45 nm CMOS technology, our approach has increased performance by 22 percent over the worst-case estimates. Also, it has decreased the correlation for the correct key by an order and has increased the probability by almost 3.5X times for wrong keys when compared with the original key to exhibit maximum correlation.
Keywords :
cryptography; power aware computing; AES S-box; CMOS technology; CPA; DPA; DVFS voltage-frequency pairs; RDVFS; aggressive designs; attackers; correlation power analysis; countermeasure; differential power analysis attacks; information leaks; maximum correlation; probability; random dynamic voltage frequency scaling; reliable designs; side-channel attacks; worst-case estimates; Clocks; Correlation; Cryptography; Delay; Registers; Reliability; Security; dynamic voltage and frequency scaling; power attacks; smart cards; timing errors;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2013.9
Filename :
6409833
Link To Document :
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