DocumentCode :
711018
Title :
Junctionless Gate-all-around pFETs on Si with In-situ doped Ge channel
Author :
I-Hsieh Wong ; Yen-Ting Chen ; Shih-Hsien Huang ; Wen-Hsien Tu ; Chih-Hsiung Huang ; Yu-Sheng Chen ; Tai-Cheng Shieh ; Liu, C.W.
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2015
fDate :
27-29 April 2015
Firstpage :
1
Lastpage :
2
Abstract :
High performance junctionless Ge Gate-all-around pFETs with fin width down to 9 nm are demonstrated. The device with the Leff of 250 nm and channel doping of 8×10 cm- has Ion/Ioff= 1×10, SS = 95 mV/dec, and Ion = 390 μA/μm. The gate controllability can be further improved with low EOT gate stack of ~ 0.7 nm for the SS down to 84 mV/dec. Junctionless devices also show higher mobility at the large VGs - Vt region than the inversion mode devices due to less dependence on surface roughness scattering. The configuration of fin width and channel concentration to achieve low SS is investigated.
Keywords :
elemental semiconductors; field effect transistors; germanium; semiconductor doping; silicon; EOT gate stack; Ge; Si; channel concentration; fin width; gate controllability; in-situ channel doping; junctionless gate-all-around pFET; surface roughness scattering; Logic gates; Performance evaluation; Rough surfaces; Scattering; Silicon; Substrates; Surface roughness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, Systems and Application (VLSI-TSA), 2015 International Symposium on
Conference_Location :
Hsinchu
Type :
conf
DOI :
10.1109/VLSI-TSA.2015.7117567
Filename :
7117567
Link To Document :
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