Analog performance of gate-first HKMG NMOS transistors — Role of device dimensions and layout

In this paper, we analyze the role of device dimensions and layout/design rules on the analog performance of HKMG NMOS transistors. We have shown ~28% improvement in the intrinsic gain and ~26% improvement in the g_m/I_d for an 80nm wide transistor compared to a 1μm wide one. We have also shown that the analog performance of transistors could be improved further by dividing a single active into multiple active fingers, by increasing the active to active spacing and by eliminating the active dummies.