Title :
Sub-50nm monolithic 3D IC with low-power CMOS inverter and 6T SRAM
Author :
Tsung-Ta Wu ; Wen-Hsien Huang ; Chih-Chao Yang ; Chein-Din Lin ; Hsing-Hsiang Wang ; Chang-Hong Shen ; Jia-Min Shieh
Author_Institution :
Nat. Nano Device Labs., Hsinchu, Taiwan
Abstract :
For the first time, a sequentially processed was demonstrated using low thermal budget processed ultrathin-body (UTB) channel technique. High-performance sub-50nm high-k/metal gate UTB MOSFETs using super-CMP-planarized laser crystallized epi-like Si ultra-thin channel (15nm) enable stackable 6T SRAMs with static noise margin (SNM) of 390 mV at operation voltage of 1V and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.
Keywords :
CMOS integrated circuits; MOSFET; SRAM chips; elemental semiconductors; invertors; low-power electronics; silicon; three-dimensional integrated circuits; 6T SRAM; Si; UTB MOSFET; low thermal budget processed ultrathin-body channel technique; low-power CMOS inverter; monolithic 3D IC; static noise margin; super-CMP-planarized laser crystallized epi-like ultra-thin channel; voltage 1 V; voltage 390 mV; CMOS integrated circuits; Logic gates; MOSFET; Random access memory; Silicon; Three-dimensional displays; Threshold voltage;
Conference_Titel :
VLSI Technology, Systems and Application (VLSI-TSA), 2015 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-TSA.2015.7117585
