Title :
Low-cost 3DIC process technologies for wide-I/O memory cube
Author :
Jui-Chin Chen ; Erh-Hao Chen ; Pei-Jer Tzeng ; Cha-Hsin Lin ; Chung-Chih Wang ; Shang-Chun Chen ; Tzu-Chien Hsu ; Chien-Chou Chen ; Yu-Chen Hsin ; Po-Chih Chang ; Yiu-Hsiang Chang ; Tzu-Kun Ku
Author_Institution :
Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
Low-cost 3DIC process approaches are investigated in terms of 3D stacking method and TSV process integration scheme. The permanent and bumpless wafer-to-wafer (PBWW) bonding technology can be applied to the DRAM wafers in the wide-I/O memory cube application. Backside TSV process with its electrical characteristics is also studied. The combination of these two process technologies can further lower the overall process cost and speed up the mass production.
Keywords :
DRAM chips; three-dimensional integrated circuits; wafer bonding; 3D stacking method; 3DIC process; DRAM wafers; TSV process integration scheme; backside TSV process; permanent and bumpless wafer-to-wafer bonding technology; wide-I/O memory cube; Bonding; Films; Scanning electron microscopy; Shape; Stacking; Stress; Three-dimensional displays;
Conference_Titel :
VLSI Technology, Systems and Application (VLSI-TSA), 2015 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-TSA.2015.7117589
