A 20GHz Class-C VCO using noise sensitivity mitigation technique

Author

Kimura, Kento ; Okada, Kenichi ; Matsuzawa, Akira

Author_Institution

Dept. of Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan

fYear

2015

fDate

26-28 Jan. 2015

Firstpage

80

Lastpage

82

Abstract

This paper presents a Class-C VCO with noise sensitivity mitigation technique. Class-C VCO has a large parasitic capacitances between gate and source nodes and this capacitance variation causes a large frequency sensitivity to noise voltage. As a consequence, the noise from gate node become the largest noise contributor. Proposed technique can control this sensitivity by tuning the tail impedance. A 65 nm CMOS prototype of the VCO demonstrates oscillation frequency from 19.35 to 22.36 GHz, the phase noise of -105.8 dBc/Hz at 1 MHz offset with power dissipation of 8.7 mW and Figure-of-Merit of -182.4 dBc/Hz.

Keywords

CMOS integrated circuits; MMIC oscillators; field effect MMIC; integrated circuit noise; phase noise; voltage-controlled oscillators; CMOS; class-C VCO; frequency 19.35 GHz to 22.36 GHz; frequency sensitivity; gate nodes; noise sensitivity mitigation technique; oscillation frequency; parasitic capacitances; phase noise; power 8.7 mW; power dissipation; size 65 nm; source nodes; tail impedance; Capacitance; Logic gates; Phase noise; Sensitivity; Transistors; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2015 IEEE 15th Topical Meeting on

Conference_Location

San Diego, CA

Type

conf

DOI

10.1109/SIRF.2015.7119881

Filename

7119881