DocumentCode
711723
Title
System design considerations for a PSSS transceiver for 100Gbps wireless communication with emphasis on mixed signal implementation
Author
Javed, Abdul Rehman ; Scheytt, J. Christoph ; KrishneGowda, Karthik ; Kraemer, Rolf
Author_Institution
Heinz Nixdorf Inst., Univ. of Paderborn, Paderborn, Germany
fYear
2015
fDate
13-15 April 2015
Firstpage
1
Lastpage
4
Abstract
Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology which is gaining interest for both wireless and wired multi-gigabit communication systems. PSSS is well suited for mixed signal transceiver implementation including channel equalization and allows for a reduction in power dissipation by avoiding high speed data converters. The architecture of a mixed signal baseband processor for 100 Gbps wireless communication is described that reduces the implementation complexity and results in a consequent reduction in power dissipation and chip area.
Keywords
spread spectrum communication; transceivers; PSSS transceiver; bit rate 100 Gbit/s; channel equalization; high speed data converters; mixed signal transceiver implementation; parallel sequence spread spectrum; physical layer baseband technology; power dissipation; wireless communication; Baseband; Correlators; Frequency modulation; Frequency synchronization; Logic gates; Barker code; PSSS; chip weighting; integrate and dump correlator; maximum length sequence (MLS); mixed signal transceiver;
fLanguage
English
Publisher
ieee
Conference_Titel
Wireless and Microwave Technology Conference (WAMICON), 2015 IEEE 16th Annual
Conference_Location
Cocoa Beach, FL
Type
conf
DOI
10.1109/WAMICON.2015.7120419
Filename
7120419
Link To Document