Title :
A DST Hardware Structure of HEVC
Author :
Jianghan Nan ; Ningmei Yu ; Wei Lu ; Dongfang Wang
Author_Institution :
Dept. of Electron. Eng., Xi´an Univ. of Technol., Xi´an, China
Abstract :
HEVC (High Efficiency Video Coding) is a new generation of video coding standard which is proposed by ITU-T VCEG and ISO/IEC MPEG for the increasingly widespread application of high-definition video. On the basis of original DCT transform of H.264, HEVC has proposed a DST transform with the size of 4×4. We design the hardware structure of pipelined DST by analyzing software algorithm, according to the parallel characteristics of the ASIC, only with shifters, addition, counters and 4-2 compression method. After logic synthesis using SMIC 0.13μm standard cell library, simulation results show that the proposed architecture of 4×4 DST logic gates for 7K. The design can meet the demanding of timing sequence under the circumstance of real-time processing of 3840×2160@25fps sequences of images under 300MHz, and is very suitable for VLSI HD encoder.
Keywords :
VLSI; adders; counting circuits; data compression; discrete cosine transforms; image sequences; logic design; video coding; 4-2 compression method; ASIC parallel characteristics; DCT transform; DST hardware structure; DST logic gates; DST transform; H.264; HEVC; ISO-IEC MPEG; ITU-T VCEG; SMIC standard cell library; VLSI HD encoder; frequency 300 MHz; high-definition video; high-efficiency video coding; image sequences; logic synthesis; real-time processing; software algorithm; timing sequence; video coding standard; Collaboration; Discrete cosine transforms; Hardware; ISO; Very large scale integration; Video coding; 4-2 Compressor; DST; HEVC; VLSI;
Conference_Titel :
Information Science and Control Engineering (ICISCE), 2015 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4673-6849-0
DOI :
10.1109/ICISCE.2015.127
