Modeling spatial and energy oxide trap distribution responsible for NBTI in p-channel power U-MOSFETs

Author

Tallarico, Andrea N. ; Sangiorgi, Enrico ; Fiegna, Claudio ; Magnone, Paolo ; Barletta, Giacomo ; Magri, Angelo

Author_Institution

DEI-“Guglielmo Marconi”, Univ. of Bologna, Cesena, Italy

fYear

2015

fDate

10-14 May 2015

Firstpage

153

Lastpage

156

Abstract

In this paper, we present a combined measurement/simulation method, implemented in order to estimate the spatial and energy oxide trap distribution induced by negative bias temperature instability (NBTI) stress in p-channel power U-MOSFETs. The methodology consists in analyzing the recovery phase at different bias conditions and correlating the results with TCAD numerical simulations. We found an oxide trap distribution positioned between 2.24 and 3.04 nm distant from oxide/channel interface with an energy level confined in the silicon bandgap.

Keywords

negative bias temperature instability; power MOSFET; semiconductor device models; technology CAD (electronics); NBTI; TCAD numerical simulations; bias conditions; energy level; energy oxide trap distribution; negative bias temperature instability stress; oxide/channel interface; p-channel power U-MOSFET; recovery phase; silicon bandgap; Energy states; Logic gates; MOSFET; Silicon; Stress; Temperature measurement; Threshold voltage; Negative bias temperature instability; TCAD simulations; U-MOSFET; oxide charge trapping/de-trapping; recovery mechanisms; stress/recovery conditions;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices & IC's (ISPSD), 2015 IEEE 27th International Symposium on

Conference_Location

Hong Kong

ISSN

1943-653X

Print_ISBN

978-1-4799-6259-4

Type

conf

DOI

10.1109/ISPSD.2015.7123412

Filename

7123412