Advanced low power RISC processor design using MIPS instruction set

Present era of SOC´s comprise analog, digital and mixed signal components housing on the same chip. In this environment processor plays a vital role. As the technology shrinking to sub-micrometer technology node, there exists a huge scope of undesirable hazards in processors. These hazards may lead to disturbance in area, power and timing which deviate from desired quantities. Our paper focuses mainly to solve some of these issues. In-order to tackle these problems, we are introducing the enhanced version of MIPS. Microprocessor without Interlocked Pipeline Stages (MIPS) is a recent architecture into the semi-conductor industry. This paper totally concentrates on designing the architecture in Verilog HDL. The design had been simulated and synthesized in Nc-launch and RTL-compiler licensed by cadence Inc respectively. The physical design of synthesized architecture had been carried on by Socencounter under slow.lib library of TSMC Cmos 180nm technology node.